Field of the Invention
The present invention relates to an image processing apparatus and a method for controlling the same, and a storage medium.
Description of the Related Art
Reconfigurable circuits such as a PLD (Programmable Logic Device), FPGA (Field Programmable Gate Array) and the like that have changeable logic circuit arrangements are well known. Typically, change of logic circuits of a PLD or an FPGA can be realized by, at the time of power activation, writing circuit configuration information stored in a non-volatile memory such as a ROM or the like in a configuration memory, which is a volatile memory inside the PLD or the FPGA. Also, because information in a configuration memory is cleared at the time of shutting down the power, it is necessary to again write the circuit configuration information that is stored in the ROM, to the configuration memory when the power is turned on. A method for configuring logic circuits of a PLD or an FPGA once in a state in which the power is supplied in this manner is called static reconfiguration. In contrast, an FPGA and the like whose logic circuit arrangement can be dynamically changed while the logic circuit is operating have been developed, and a method for dynamically changing logic circuits in this manner is called dynamic reconfiguration.
Also, there is an FPGA in which a circuit arrangement in a specific region can be rewritten instead of rewriting the circuit arrangement of the entire FPGA tip, and such rewriting is called partial reconfiguration. In particular, the changing of a circuit arrangement of a circuit other than operating circuits without stopping the operations thereof is called dynamic partial reconfiguration. In dynamic partial reconfiguration, logic circuits of an FPGA can be partially reconfigured by rewriting only a partial region of the configuration memory at the time of dynamic reconfiguration instead of rewriting the entire configuration memory. It is possible to implement a plurality of logic circuits that are switched in a time-sharing manner in a given region of an FPGA, for example, by using such a dynamic partial configuration. As a result, application-specific functions can be flexibly realized with limited hardware resources while keeping high-speed operation performance of hardware.
Such FPGAs whose circuit arrangement can be dynamically changed (rewritten) require a long time for rewriting the circuit arrangement, and the time is proportional to the size of the circuit configuration information that is to be written in the configuration memory. Therefore, conventionally, a technique has been proposed in order to reduce the time required to rewrite a circuit arrangement. For example, Japanese Patent Laid-Open No. 2011-186981 proposes a technique in which on a reconfigurable circuit, when a plurality of partial circuits that constitute a pipeline that executes data processing in order are reconfigured, reconfiguration is performed in order beginning with the first partial circuit in the pipeline, and the reconfigured partial circuits are started in order. Accordingly, higher-speed data processing is realized than with a method for reconfiguring and starting reconfigurable circuits altogether at the same time on the reconfigurable circuit.
Also, image processing apparatuses such as an MFP (Multi Function Printer) and the like execute image processes that are selected in accordance with a request from a user, from among a plurality of executable processes (a copy job, a print job, a send job and the like). Each image process is realized by hardware or software. Typically, operations and process content to be performed by hardware logic circuits when required to realize each image process are set by parameters given for the logic circuits.
In an image processing apparatus that includes a reconfigurable circuit in which a plurality of partial circuits can be dynamically reconfigured in a pipeline configuration, in the case where each of the plurality of partial circuits is reconfigured as a circuit (an image processing unit) that executes a separate image process, the following issues arise. In such image processing apparatuses, for each of a plurality of image processing units, parameters for determining operations and process content of the image processing unit need to be set for the image processing unit after reconfiguration of the image processing unit has been completed. Thus, even if reconfiguration and startup of the image processing unit have been completed, an image process cannot be initiated until the setting of parameters is completed. Therefore, in such image processing apparatuses, in order to allow an image process to be initiated sooner after the image processing unit is reconfigured, it is necessary to shorten the time required to set parameters for the image processing unit.